|
Abstract:The efficiency of an 8-bit flash analog-to-digital converter (ADC) is influenced by
factors such as power consumption, area, and timing. As technology advances, the
demand for better performance and higher standards in chip design technologies is
increasing. As technology continues to advance, the standards for chip performance
will likely rise, motivating researchers and manufacturers to strive for 5G and even
greater achievements. The aim of this work is to study and analyse the performance
requirements in terms of area, power consumption, and speed of 8-bit flash analogto-Digital Converter. Compared to other kind of analog-to-digital converters, flash
converters have a significantly greater conversion rate. The number of comparators
needed for flash converters is more 2
N
-1 for N-bit in the conventional design
architecture and consumes more power and area. In order to reduce the design
complexity, power, area and noise for high bit resolution in the high-speed flash
analog-to-digital converter architecture, this new design focuses on employing
multiplexers to reduce the number of comparators and parameters. The traditional
Flash type ADC uses more power and takes up more chip space since it needs 255
comparators for 8-bit flash. Therefore, reducing the number of comparators and
noise are the design's primary goal. Only 65 comparators are needed for the
construction of the 8-bit resolution Flash ADC employing multiplexers with
evolution parameters such power dissipation 21uW, maximum noise
1.251nv**2/Hz, offset voltage 69.2103mv, SNDR 49.2dB, SFDR 61.3dB,
differential non-linearity 0.41 LSB and INL (Integral non-linearity) 0.5 LSB. The
design simulation carried out using cadence virtuoso. The work focused on backend
design using 180nm CMOS process Technology.
|