The significant expansion of data-intensive multimedia applications over communication networks has posed new challenges in security. As text, image, and video streams are increasingly transmitted over open networks in real-time, ensuring confidentiality, integrity, and authentication has become more complex. From this perspective, in this paper, we present an optimized design and ASIC implementation of QMC-Crypto, a QoS-aware multi-core cryptographic processor tailored for high-throughput multimedia security. QMC-Crypto integrates dedicated cryptographic cores for AES, SHA-2, ECC, and a Grain-based keystream generator, supporting multiple configurable security modes, including confidentiality, integrity, authentication, and combined services (e.g., confidentiality + integrity, decryption + signature verification). To optimize power efficiency, latency, and memory performance, we have adopted a bottom-up approach based on coherent, interdependent architectural layers of efforts. We propose (1) a shared-buffer memory architecture to alleviate data redundancy and latency; (2) a dynamic QoS-aware task scheduling scheme to intelligently allocate resources; and (3) a Globally Asynchronous Locally Synchronous (GALS) clocking scheme to improve power efficiency and enhance resistance against timing-based side channel attacks. These efforts are complemented by additional design optimizations such as adaptive buffer scaling, minimalist task scheduling control logic, selective core activation, and compact ROM utilization, all aimed at achieving a performance-driven and resource-efficient final ASIC implementation. Finally, the QMC-Crypto was successfully validated by VHDL/Simulink co-simulation and fully implemented in ASIC using 0.5 µm CMOS technology, demonstrating real-time performance, low dynamic power, and a compact silicon footprint, making it suitable for secure multimedia processing in embedded systems.